1. Field
The embodiments relates to semiconductor integrated circuits and testing methods.
2. Description of the Related Art
FIG. 1 is a diagram showing a major portion of one example of a known semiconductor integrated circuit. As shown in FIG. 1, an LSI (large scale integrated) circuit 1 has a boundary scan chain 2, system circuits 3-1 to 3-4, an input/output (IO) cell 4, and an IO pad 5. The boundary scan chain 2 has flip flops (FF1 to FF5) 6-1 to 6-5 that constitute a register (or a boundary scan register) for realizing a boundary scan testing function. A scan test clock STCLK is input to clock input terminals of the flip flops 6-1 to 6-5, and a path control signal PCNT is input from the flip flop 6-5 to a control terminal of the IO cell 4 via the system circuit 3-4. An external load (not shown) is connected between the IO pad 5 and ground.
In propagation delay testing (or transition delay testing), a high-speed, i.e., a short-duration, scan test clock STCLK is input to detect a propagation delay failure in the data path of the flip flops 6-1 to 6-5. The scan test clock STCLK has a frequency of, for example, about 100 MHz. A path captured during such propagation delay testing includes, for example, the system circuits 3-1 to 3-3 and the IO cell 4.
FIG. 2 is a diagram showing a known IO cell and its peripheral structure. As shown in FIG. 2, when a path 500 including an IO cell 4 is to be subjected to propagation delay testing, an influence of an external load 8 during the testing of the LSI circuit 1, i.e., a load (capacity) of a testing device, appears as path delay and signal reflection, as indicated by the black arrow, since the IO cell 4 exists along the path 500. Since the load of the testing device is larger than the external load 8 during normal operation of the LSI circuit 1, the amount of time of delay in the path 500 including the IO cell 4 during the testing is also larger than the amount of time of delay in the path 500 during the normal operation. Thus, the delay acts as a factor for reducing the operating frequency of the propagation delay testing. In FIG. 2, the path 500 captured during the propagation delay testing includes the system circuits 3-2 and 3-3, and the flip flop 6-3 serves as the start point of the path 500 and the flip flop 6-4 serves as the end point of the path 500.
For example, Japanese Unexamined Patent Application Publication No. 8-62298 discloses a semiconductor integrated circuit having a selector that loops back input data of a high-speed interface to an output section. Japanese Unexamined Patent Application Publication No. 10-26654 discloses a technology in which an input characteristic of a terminal having an input function is tested independently of the state of another input terminal and the logic of an internal circuit.
The known semiconductor integrated circuits, however, have a problem in that it is difficult to perform propagation delay testing without influence of an external load.